| Port | Description |
|---|
| abc | system for sequential logic synthesis and verification |
| clipper2 | library to perform boolean operations on polygons |
| coil64 | inductance coil calculator |
| dxf2gcode | tool to convert 2D (dxf, pdf, ps) files to gcode |
| freecad | general purpose parametric 3D CAD modeler |
| fritzing | interactive electronics designing software |
| geda-gaf | suite of tools for electronic design automation |
| gerbv | viewer for Gerber (RS-274X) files |
| gnucap | Gnu Circuit Analysis Package |
| graywolf | placement tool used in VLSI design |
| gtkwave | GTK+-based electronic waveform viewer |
| horizon-eda | electronic design automation package |
| kicad | schematic and PCB editing software |
| lepton-eda | lepton electronic design automation suite |
| lib3mf | implementation of the 3D Manufacturing Format file standard |
| librecad | 2D CAD program |
| magic | interactive system for VLSI circuit layouts |
| manifold | geometry library for topological robustness |
| necpp | NEC2++ antenna simulator |
| netgen | tool for netlist comparison (LVS) and format manipulation |
| netgen-mesher | automatic 3d tetrahedral mesh generator |
| opencascade | platform for 3D CAD, CAM, and CAE |
| openscad | programmers solid 3D CAD modeller |
| opensta | Parallax Static Timing Analyzer |
| pcb | printed circuit board layout tool |
| pcb2gcode | tool for isolation, routing, and drilling of PCBs |
| prusaslicer | g-code generator for 3D printers |
| qcad | Qt-based 2D CAD system |
| qelectrotech | electric diagrams drawing tool |
| qflow | full end-to-end digital synthesis flow for VLSI ASIC designs |
| qrouter | multi-level, over-the-cell maze router for VLSI design |
| solvespace | parametric 2D/3D CAD program |
| tkgate | Tcl/Tk based digital circuit editor and simulator |
| xcircuit | circuit drawing and schematic capture |
| xnec2c | graphical NEC2 antenna simulator |
| xnecview | NEC2 antenna simulator visualizer |
| xschem | hierarchical schematic capture program |
| xtrkcad | CAD program for designing model railroad layouts |
| yosys | framework for Verilog RTL synthesis |